A conventional buffer circuit configuration 10 is illustrated in FIG. 1. An inverting input buffer circuit 12 coupled between high and low potential power rails V.sub.CCI, GNDI receives input data signals of logic high and low potential levels at the input V.sub.IN. The input buffer circuit 12 drives a passgate circuit PSGT which transmits data signals or blocks transfer of data signals from the passgate input DIN to the passgate output DL depending on the signals at the passgate enable or latch enable inputs LE,LEB. Operation of the conventional passgate circuit PSGT is described below with reference to FIG. 3.
A data signal at the output DL of passgate PSGT is latched by latchback circuit LTBK consisting of feedback coupled inverters IF1, IF2 and provides the input to the final output buffer circuit 14. Output buffer circuit 14 is a tristate output buffer circuit coupled between high and low potential power rails V.sub.CCI,GND0 for driving the final output V.sub.OUT and any load capacitance LOAD. Complementary tristate enable signal inputs OE,OEB are provided to implement the high impedance third state or tristate at the output. Such an output buffer circuit is described for example in U.S. patent application Ser. No. 796,455 referred to above.
The conventional passgate circuit PSGT following the input buffer circuit 12 is shown in further detail in FIG. 3. The passgate circuit is formed by CMOS transistors P1,N1 having primary current paths coupled in parallel. The control gate nodes of parallel coupled CMOS transistors P1,N1 are coupled respectively to complementary latch enable inputs LE,LEB. With complementary signals LE high and LEB low, neither CMOS transistor is conducting and the passgate PSGT is in the blocking mode blocking transfer of data signals from passgate input DIN to passgate output DL. With complementary signals LE low and LEB high, both CMOS transistors P1,N1 are conducting in the transparent mode for transfer of data signals.
A disadvantage of the conventional buffer circuit configuration 10 and passgate PSGT of FIGS. 1 and 3 is that current drive at the output of input buffer circuit 12 is limited by the passgate impedance. The passgate impedance introduces a propagation delay or time shift .DELTA.T for data signals passing from the input DIN to the output DL and limits the edge rate for both the falling and rising edges of the data signals. A conventional approach to overcoming the time shift .DELTA.T is to increase the power of the input buffer circuit 12. This power level may be limited by the circuit specifications however and the problem of undesirable power dissipation also arises.
In order to reduce the impedance of the passgate PSGT, large transistors P1,N1 may be used but this increases the capacitance of the "load" at the output of the input buffer circuit 12. The RC time constant of the passgate continues to adversely effect rising and falling edge rates during transfer of data signals.
A conventional bipolar input buffer circuit 12 is illustrated in further detail in FIG. 2. The example of FIG. 2 is an inverting input buffer circuit delivering low and high potential level output signals at the output V.sub.OUT in response to high and low potential level data signals at the input V.sub.IN. The output pullup and pulldown transistors are bipolar transistors. The Darlington transistor output pullup Q4,Q5 sources current to the output V.sub.OUT from the high potential power rail V.sub.CCI. The bipolar transistor output pulldown Q3 is a high current drive transistor element for sinking current from the output V.sub.OUT to the low potential power rail GND. A bipolar transistor phase splitter Q2 controls the conducting states of the respective output transistor pullup and pulldown in opposite phase in response to data signals at the input V.sub.IN.
The input V.sub.IN is coupled to the base node of phase splitter transistor Q2 through diode D1 for logic low potential level input data signals. For high potential level data signals, the input V.sub.IN turns on input transistor Q1 for providing base drive current through resistors R1 and R2 to the base node of transistor phase splitter Q2. The base node of input transistor Q1 is coupled to the input V.sub.IN through isolating PNP input transistor QP1.
With a high potential level signal at the input V.sub.IN phase splitter transistor Q2 is conducting and turns on the transistor output pulldown Q3. Discharge current passes from the output V.sub.OUT and through discharge paths R5,SD3 and SD2 to accelerate turn off of the transistor output pullup Q4,Q5 and turn on of the transistor output pulldown Q3. The transistor phase splitter Q2 is coupled to the high potential power rail V.sub.CCI through collector resistor R3 and discharges the base and turns off pullup transistor Q4. A low potential level output signal appears at the output V.sub.OUT.
With a low potential level data signal at the input V.sub.IN, the transistor phase splitter Q2 turns off and the base of transistor output pulldown Q3 is discharged through the "poor man" squaring network SD5,R4. An AC Miller killer circuit (ACMK) prevents turn on of the output pulldown transistor Q3 during the transition from low to high potential level at the output V.sub.OUT. The AC Miller killer circuit Q9,SD6,SD4,D2 is coupled to the base node of output pulldown transistor Q3 to divert capacitive feedback Miller current, a parasitic current that may pass from the collector mode to base of Q3 through the internal Schottky diode clamp during charging of output load capacitance and transition from low to high potential level at the output V.sub.OUT. The ACMK discharges the parasitic feedback Miller current to the low potential power rail GND. At the same time the transistor output pullup Q4,Q5 turns on sourcing current and establishes a high potential level output signal at the output V.sub.OUT.
A capacitor coupled transistor CQ6 may be coupled in the discharge path SD1,R7 at the base node of transistor phase splitter Q2 to control the LH edge at the input by slowing down the switching of the phase splitter. It is the output V.sub.OUT of input buffer circuit 12 that drives the passgate PSGT as shown in FIG. 1.